1. Field of the Invention
This invention relates to a manufacturing method of semiconductor devices. It is especially suitable for manufacturing non-volatile semiconductor memory devices.
2. Description of the Related Art
A memory cell transistor in a non-volatile semiconductor memory device (EPROM) hitherto has such a structure as shown in FIG. 1, for instance. A gate electrode portion 25 having a two-layer gate structure is formed on each of element regions of a semiconductor substrate (silicon substrate) 1. The gate electrode portion 25 has a first gate insulating film 3, a floating gate electrode 4, a second gate insulating film 5, a control gate electrode 6, and an insulating film 7, all of which are formed on a main surface of the semiconductor substrate 1. These elements are formed by successively placing one over another. The side walls of gate electrode portion 25 are covered with the insulating film 7. Those portions of the insulating film 7 that cover the side walls are formed by the side walls of the electrode 6 and the side walls of the electrode 4 being oxidized when the insulating film 7 is formed on the control gate electrode 6 by thermal oxidation. Impurity diffusion regions 14 and 16, which are respectively to be a source region and a drain region of a floating gate type MOS transistor, are formed in that portion of the substrate 1 that is below the gate electrode portion 25 with a channel region interposed between them. In the structure shown in FIG. 1, the impurity diffusion region 16 is commonly used by any two adjacent floating gate type MOS transistors (memory cell transistors). On the resultant structure an interlevel insulating film 21 is formed. The interlevel insulating film 21 has a plurality of contact holes 26 each at that portion that is above one of the impurity diffusion regions (the drain region 16, for instance). Metal wiring layers (aluminum wiring layers, for instance) 24 functioning as bit lines are formed over the interlevel insulating film 21 such that they contact through the contact holes 26 with the drain regions 16.
Note that, when manufacturing the above-mentioned EPROM, a field oxide film (not shown in the drawings) for element isolation is used as a reference for mask alignment. Therefore, a certain amount of margin must be allowed when mask alignment is performed to form contact holes, when the margin is not allowed, those portions of the insulating film 7 that cover the side walls of the gate electrode portion 25 may be removed by etching, and the aluminum wiring layers 24 and the control gate electrode 6, or the floating gate electrode 4, of the memory cell transistor may be short-circuited in a worst case.
Therefore, the above-mentioned conventional EPROM requires a margin between the gate electrode portion and the contact hole when mask alignment is performed. The amount of the margin is determined by the exposure system, etc. Therefore, the reduction of the space between memory cell transistors has a limit, which hinders cell miniaturization.
To solve the above problem, the present inventors had already proposed a semiconductor integrated circuit device and its manufacturing method, which realize reduction of the margin between the control gate electrode, or the floating gate electrode, and the contact hole when performing a mask alignment to make the contact hole, and promote miniaturization (Japanese Unexamined Publication No. 1-251761 corresponding to Japanese Patent Application No. 63-78980). One example of a semiconductor integrated circuit device in accordance with the above-identified application is shown in FIGS. 2A and 2B. FIG. 2A is a plan view showing a pattern, and FIG. 2B is a sectional view taken along an X-X' line of FIG. 2A for showing the sectional structure.
This semiconductor integrated circuit device comprises memory cell arrays, each having floating gate type MOS transistors. In each of the MOS transistors, a source region 14 and a drain region 16 are self-align formed with respect to a multilayer-structured pattern which is made of a floating gate electrode 4 and a control gate electrode 6. A gate electrode portion 25 has an insulating film 7 on its upper surface and an insulating film 11 on its side walls. A low concentration impurity diffusion region 15 is formed at that portion of the drain region 16 that is near the channel region. A conductive layer 19 made up of a low resistance material covers the surface of the drain region 16 and the surface of at least those portions of the insulating film 11 that are on the side walls of the gate electrode portions 25 and are located at the end of the region 16. An interlevel insulating film 21 is formed on the resultant structure. A contact hole 26 is formed in that portion of the interlevel insulating film 21 that is above the conductive layer 19. Metal wiring layers 24 are formed on the interlevel insulating film 21 and the conductive layer 19 within the contact hole 26, and the metal wiring layers 24 are electrically connected with the drain region 16.
The characteristic feature of the structure shown in FIGS. 2A and 2B is that the conductive layer 19 is interposed between the drain region 16 and the metal wiring layers 24. Namely, the conductive layer 19 protects the side walls of each gate electrode portion 25 when making the contact hole 26, so that the margin between the gate electrode portion 25 and the contact hole 26 can be made as small as possible. Therefore, miniaturization of the device can be promoted.
In the above structure, the field oxide film 2 for element isolation is discretely formed, as shown in FIG. 2A, so that the distance d between the end of the gate electrode portion 25 (the insulating films 7 and 11) and the end of the field oxide film 2 must be set carefully in consideration of the margin for mask alignment, or the width of the source region 14 will be narrow, when divergence in mask alignment occurs, and thus the element characteristics will be degraded.
As explained above, in the conventional semiconductor device manufacturing method, the margin between the gate electrode portion and the contact hole for the source or drain must be sufficiently allowed for mask alignment, so that the space between the memory cell transistors cannot be made narrow. If it is made narrow, the element characteristics will be degraded.